Projekt ASCB / ASCB-II

Moderatoren: Sleeπ, andymanone

Burkhard
Beiträge: 488
Registriert: 03.06.2021 21:29
Has thanked: 10 times
Been thanked: 39 times
Kontaktdaten:

Re: Projekt ASCB / ASCB-II

Beitrag von Burkhard »

Ich wollte auch nur @skr einen kleinen Gedankenstoß geben, selber benötige ich sowas auch nicht ...

Benutzeravatar
pancio
Beiträge: 318
Registriert: 31.08.2021 07:31
Has thanked: 299 times
Been thanked: 306 times
Kontaktdaten:

Re: Projekt ASCB / ASCB-II

Beitrag von pancio »

HiassofT hat geschrieben:
11.02.2026 16:06
mega-hz hat geschrieben:
11.02.2026 15:27
SIO: CLOCK-IN und CLOCK-OUT

welche Geräte benutzen diese Leitungen und welche Vorteile/Möglichkeiten hat man damit?
Clock-Out wird IIRC vom SIO2USB (von der RAF) und von der Indus Floppy verwendet um die Übertragungsrate zu ermitteln.

Clock-In ist in Wirklichkeit "Bidirectional Clock", kann also sowohl Ein- als auch Ausgang sein (je nach Modus der in SKCTL konfiguriert ist).

so long,

Hias

Hi Guys,

CLK_IN/CLK_OUT signals are also found in the CA2001/LDW2000 drives, which are almost faithful clones of the IndusGT, but I've never encountered their use. I'm very disappointed by this, because synchronous transmission allows for enormous possibilities. And it's not just about speed! An example is loading data while simultaneously playing music on POKEY.

Theoretically, it's possible to achieve speeds much higher than 125 kbps because we're not limited by the AUDF4 register. A few weeks ago, I ran tests in synchronous mode at speeds exceeding 300 kbps using an ESP32-S3, and the results were promising.

And why did Atari abandon the idea of ​​using synchronous mode for higher speeds? This is likely due to a bug in the POKEY structure—the received bit is shifted in the buffer due to interference from the PHI2 clock. This issue is currently being investigated, and the well-known programmer @foft is trying to fix this POKEY bug in PokeyMax :-) If successful, transmissions of ~400 kbps will be possible.

There's another reason why synchronous mode wasn't used: the schematic (e.g., CA2001) indicates that the CLK_IN/CLK_OUT signals are fed from the data bus via the 74LS244, which means that each bit and clock cycle is sent using the BIT-BANG method (must be prepared by the CPU), which could be a bottleneck for the entire transmission process. These are just my guesses, but they seem plausible. If you have any information, please share it, as I'm also working on using synchronous mode...
Dateianhänge
CA2001sch.png
CA2001sch.png (666.72 KiB) 9 mal betrachtet
pancio

https://systemembedded.eu
PTODT / A.B.B.U.C. Member

Antworten

Wer ist online?

Mitglieder in diesem Forum: Erhard, Matti70 und 1 Gast